Project involved design and verification project of a configurable I/O bridge. External I/O interfaces for the I/O bridge included SATA, PATA, USB1.1, USB2.0, FEC, I2C, I2S, UART, AC97, FMC. QualCore was involved in RTL development, verification, FPGA porting and system verification

Verification Approach

· Verification environment included BFMs for Xtensa Processor, SDRAM and all the I/O interfaces mentioned above,   Bus Monitors and Checkers. QualCore's portfolio of existing verification IP was leveraged

· Bottom-up verification was followed

- Level 1: Verification of all individual blocks in isolation
- Level 2: Verification of system memory map and internal interconnect of the design
- Level 3: Verification of system level basic functionality
- Level 4: Verification of system through corner cases and boundary conditions

· Stimulus application to BFMs through a command interpreter, which was internally developed in C. A basic set of   commands were defined, which were interpreted into hexadecimal format and fed to BFMs as inputs.