Openings: USA || INDIA
Careers - India

Mixed-Signal Engineer (Characterization & model generation – Verilog and IBIS) (Code: IN130)
Qualification:
B.E. / B.Tech in ECE
Experience:
Minimum 1 years of experience
Key Skills:
Verilog, Digital Design, Circuit Design
Responsibilities:
Characterization of digital standard cells, IO cells
IBIS (IO Buffer Information Specification) model generation
Verilog model generation
Requirements:
Should have a good understanding of CMOS circuits and logic design
Should have good understanding of Synthesis and Timing Analysis
Should have good command over Verilog
Knowledge of Design Compiler and Primetime is a plus
Knowledge of Spice and Verilog-A will be an advantage
Location: Hyderabad, India
Please send your resume to hr@qualcorelogic.com with the relevant code in the subject.
HRD - Recruitment
QualCore Logic Ltd.
7-145 Nagendra Nagar,
Habsiguda,
Hyderabad - 500 007
India
  

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