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B.Tech or M.Tech in EE |
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Experience: |
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Minimum 2 year of experience |
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Key Skills: |
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DFT, Verilog Simulation, Scripting |
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Responsibilities: |
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Generating and debugging manufacturing test programs for Flash based FPGA
families |
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Generating and running Logic Validation test for FPGA |
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Improving and extending existing manufacturing tests to other FPGA family
members |
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Test debugging and failure analysis |
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Software Validation |
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| Requirements: |
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Logic Testing & Design-for-Testability (Test Generation, Fault Simulation
Methodologies, Scan Design, Signature Analysis) |
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Boundary Scan |
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Hardware description languages (Verilog and VHDL) |
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ASIC/FPGA design flow and methodology (HDL, synthesis, static timing analysis,
constraining, place & route) |
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Programming/software skills in C/C++ |
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Basic knowledge of semiconductor technologies |
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Unix, Make, Revision Control (CVS), Perl, TCL |
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Must be able to document work by writing test plan and test reports |
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Knowledge in FPGA architectures, Analog and mixed signal circuit design, is a
plus |
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Basic Knowledge on Manufacturing Test Systems (like Teradyne J750) is a plus |
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Experience with JAVA is a plus |
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Strong analytical and problem solving skills |
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| Location: Hyderabad, India |
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| Please send your
resume to hr@qualcorelogic.com with
the relevant code in the subject. |
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HRD
- Recruitment
QualCore Logic Ltd.
7-145 Nagendra Nagar,
Habsiguda,
Hyderabad - 500 007
India
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