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B.Tech/M.Tech in Electronics and Communications/Electrical and Electronics |
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Experience: |
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2+ years of experience as Digital Front End Engineer |
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Key Skills: |
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Verilog/VHDL |
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RTL verification |
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Logic Synthesis |
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Static Timing Analysis |
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Equivalence Checking |
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Perl and Shell Scripting |
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Responsibilities: |
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Supporting Static Timing Analysis and Logic Synthesis tools like PrimeTime and DC-Compiler |
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 | Generating Test Bench and performing automated simulation |
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 | Simulations, verifications and debugging for logic design (RTL and Netlist) |
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 | Documenting the Specification, Implementation and Verification |
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Requirements: |
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Hands on experience with tools like PrimeTime, DC-Compiler, NC-Verilog etc., |
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Hands on experience with Static Timing analysis at gate level which includes timing fixes |
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Working knowledge of ASIC design flow, VHDL or Verilog |
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Working experience with Digital Mixed-Signal systems is a plus |
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Industry experience with 90nm and/or 65nm technologies is a strong plus |
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Perl and Shell scripting is a plus |
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Must have strong self learning ability, leadership and enjoy working in teams |
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Strong analytical and problem-solving skills |
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Excellent communication, documentation and presentation skills |
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| Location: Hyderabad, India |
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| Please send your
resume to hr@qualcorelogic.com with
the relevant code in the subject. |
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HRD
- Recruitment
QualCore Logic Ltd.
7-145 Nagendra Nagar,
Habsiguda,
Hyderabad - 500 007
India
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