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B.E / B.Tech or M.E / M.Tech in EE |
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Experience: |
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Minimum 3 years of experience |
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Key Skills: |
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Verilog, VHDL, Verification, Coverage, Debugging, Documentation |
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Responsibilities: |
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Develop Behaviour Model for our FPGA blocks using High-Level specs |
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Develop testbench to verify all the features document in the specs |
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Develop testbench to verify Behaviour models delivered by IP vendors |
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Write verification plan to verify the blocks silicon implementation |
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Implement verification plan using Verilog Simulation |
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| Requirements: |
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Logic Testing |
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Strong analytical and problem solving skills |
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Hardware description languages (Verilog and VHDL) |
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ASIC/FPGA design flow and methodology (HDL, synthesis, static timing analysis,
constraining, place & route) |
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Programming/software skills in C/C++
or Java |
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Unix, Make, Revision Control (CVS), Perl, TCL |
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Must be able to document work by writing test plan and test reports |
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Basic knowledge of semiconductor technologies |
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Strong analytical and problem solving skills |
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Knowledge in FPGA architectures is a plus |
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Knowledge in Analog and Mixed signal circuit design is a plus |
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| Location: Hyderabad, India |
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| Please send your
resume to hr@qualcorelogic.com with
the relevant code in the subject. |
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HRD
- Recruitment
QualCore Logic Ltd.
7-145 Nagendra Nagar,
Habsiguda,
Hyderabad - 500 007
India
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