Adhering to PCI Express standard bus specification 1.0 A, V6210 is a configurable core optimized for link utilization, latency, reliability and offers a silicon footprint for ASIC implementations.  It incorporates the Transaction Layer, Data Link Layer and Physical Layer of the PCI Express protocol into a synthesizable core available for Verilog.

“Our skillful team leveraged its experience to design this core to be high performance and reliable, offering low latency and low gate count,” says Mahendra Jain, president of QualCore Logic.  “The addition of this core expands our offerings and enables us to fully support the bus interface area, a growing segment of system-on-chip design.”

Pricing and Availability

V6210 is available now and is priced at $150,000.  Contact QualCore Logic at (408) 541-0730 or via email at sales@qualcorelogic.com.

About QualCore Logic

Founded in 1994, QualCore Logic provides ASIC design implementation and delivery of packaged and tested digital, mixed-signal and analog systems-on-chip (SoCs), based on silicon-proven IP.  It can take an engineering or register transfer level (RTL) specification to GDSII through final silicon, and has designed 10-million gate chips implemented in .13 micron and other process technologies.  It operates design and support centers in Sunnyvale, Calif., Plano, Texas, and Hyderabad, India.  Corporate headquarters is located at:  1289 Anvilwood Avenue, Sunnyvale, Calif.  94089.  Telephone:  (408) 541-0730.  Facsimile:  (408) 541-0731.  Email:  sales@qualcorelogic.com.  Web Site:  http://www.qualcorelogic.com/

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