Remarks Mahendra Jain, QualCore Logic’s president and chief executive officer (CEO):  “QualCore Logic’s strategy is to build the largest and most diverse portfolio of silicon-validated analog and mixed-signal IP and special I/Os.  These 15 new IP cores bring that number to more than 400.”

The 15 analog IP cores and special I/Os are available in the 0.13-micron 1.0v/3.3v process technology and are delivered as GDS II files.  They support the video/imaging (see Figure 1), memory/graphics (see Figure 2) and peripheral computing interface (see Figure 3) markets.  (See note at the end of the news release for details on getting copies of these figures.)

The Video Imaging IP consists of a 10-bit, 350 MHz triple video Digital to Analog Converter (DAC) designed to drive Red-Green-Blue Video Signals of display monitors and a 15 to 350 MHz video phase-locked loop (PLL) is designed to provide the clock.

Memory/Graphics IP satisfies the needs of project teams designing products to interface with double-data-rate (DDR) SDRAM memories and Graphic DDR memories.  The first in this category is a 500 MHz SSTL I/O available to operate in a class I, class II or GDDR-II mode using the built-in On Die Termination (ODT) for calibration of internal terminations over Process, Voltage and Temperature (PVT).  A matching 250 to 500 MHz analog double-data-rate (DLL) is available with separate master and slave cells. Having separate slave DLL cells allows it to be physically located close to separate Strobe Signals of the DDR applications, improving the signal integrity of the high-speed designs. A 250 to 1650 MHz high-speed PLL is available and can be used to generate the master clock for DDR and digital visual interface (DVI) systems.

The peripheral computing interface IP is used in the Advanced Graphics Port (AGP) market.  A 533 MHz AGP 8x I/O has been designed to operate in 1x, 2x, 4x and 8x modes and uses an on-chip calibration technique for eliminating PVT dependencies.  It works with a 66 to 533 MHz AGP PLL.

Finally, a few miscellaneous cells are available such as a PCI 2.3 I/O, a 300 MHz class I SSTL I/O, various crystal oscillators and a complete I/O library compatible with all of the special I/Os.

Each IP core is compliant with various graphics and memory interface specifications.  Deliverables include:  GDS II stream files, Spice netlist for layout versus schematics (LVS) verifications; design rule checks (DRC) and LVS verification reports and layer mapping file in text format; Library Exchange Format (LEF) footprint data; Verilog behavioral and .lib models.


Availability 

All cores are available now for licensing.  Pricing is available upon request. 

For more details, visit the QualCore Logic website located at:  http://www.qualcorelogic.com.  Or, contact its Sales Department at (408) 541-0730, Ext. 205, or sales@qualcorelogic.com

About QualCore Logic

Founded in 1994, QualCore Logic is a leading provider of digital, mixed-signal and analog IP for system-on-chip (SoC) designs.  It can take an engineering or register transfer level (RTL) specification to GDSII through final silicon.  It operates design and support centers in Sunnyvale , Calif. , and Hyderabad , India , with more than 150 design engineers.  Corporate headquarters is located at:  1289 Anvilwood Avenue , Sunnyvale , Calif.   94089.  Telephone:  (408) 541-0730.  Facsimile:  (408) 541-0740.  Email:  sales@qualcorelogic.com.  Web Site:  http://www.qualcorelogic.com/

Note to editors:

A Powerpoint file with figures 1-3 that illustrate QualCore Logic’s capabilities for video/imaging, memory/graphics and peripheral computing interface is available upon request.  

Contact:

Nanette Collins

(617) 437-1822 nanette@nvc.com  

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